----------------------------------------------------
-- Implemetacion de un registro de memoria de 8 bits
-- Amilcar J., Erazo P.
----------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--Entidad registro de 12 bits

entity pipeline_cu_vrf is
    port (
        INPUT_i  : in std_logic_vector (4 downto 0);
        CLK_i	 : in std_logic;
        OUTPUT_o : out std_logic_vector (4 downto 0));
end pipeline_cu_vrf;

--------------------------------------

architecture behavioral of pipeline_cu_vrf is

	component reg5bits is
		port (
			D_i   : in  std_logic_vector (4 downto 0);
			CLK_i : in  std_logic;
			Q_o   : out std_logic_vector (4 downto 0));
	end component;

	signal w0,w1,w2,w3,w4 : std_logic_vector(4 downto 0);

	begin
		U0 : reg5bits port map ( INPUT_i, CLK_i, w0 );
		U1 : reg5bits port map ( w0 , CLK_i, w1 );
		U2 : reg5bits port map ( w1 , CLK_i, w2 );
		U3 : reg5bits port map ( w2 , CLK_i, w3 );
		U4 : reg5bits port map ( w3 , CLK_i, w4 );
		U5 : reg5bits port map ( w4 , CLK_i, OUTPUT_o);
end behavioral;

-- vim: tabstop=4 : shiftwidth=4 : expandtab
